1. Field of the Invention
The present invention relates to a method for producing a semiconductor device having surrounding gate MOS transistors (SGTs).
2. Description of the Related Art
In recent years, the use of SGTs as semiconductor elements that provide highly integrated semiconductor device has become widespread. With this background, higher integration of semiconductor devices having SGTs has been desired.
FIG. 13 shows a complementary metal-oxide-semiconductor (CMOS) inverter circuit having typical metal-oxide-semiconductor (MOS) transistors. As shown in FIG. 13, this circuit is constituted by an N-channel type MOS transistor 100a and a P-channel type MOS transistor 100b. A gate 101a of the N-channel type MOS transistor 100a and a gate 101b of the P-channel type MOS transistor 100b are connected to an input terminal Vi. A source 102a of the N-channel type MOS transistor 100a and a source 102b of the P-channel type MOS transistor 100b are connected to an output terminal Vo. A drain 103b of the P-channel type MOS transistor 100b is connected to a power supply terminal Vdd. A drain 103a of the N-channel type MOS transistor 100a is connected to a ground terminal Vss. In this circuit, in response to the application of an input voltage corresponding to “1” or “0” to the input terminal Vi, an output voltage corresponding to inverted “0” or “1” is taken out from the output terminal Vo. Such a CMOS inverter circuit is used in various circuit chips such as microprocessors. The realization of highly integrated CMOS inverter circuits directly results in the reduction in the size of circuit chips such as microprocessors. This reduction in the size of circuit chips realizes the reduction in the cost of the circuit chips.
FIG. 14 is a view showing a cross-sectional structure of a planar CMOS inverter circuit in the related art. As shown in FIG. 14, an N-well region 105 (hereinafter, a semiconductor region that forms a P-channel MOS transistor and contains a donor impurity is referred to as “N-well region”) is formed in a P-type semiconductor substrate 104 (hereinafter, a semiconductor substrate containing an acceptor impurity is referred to as “P-type semiconductor substrate”). Element isolation insulating layers 106a and 106b are formed between a surface layer portion of the N-well region 105 and a surface layer portion of the P-type semiconductor substrate 104. Furthermore, a gate oxide film 107a for a P-channel MOS transistor is formed on a surface of the N-well region 105, and a gate oxide film 107b for an N-channel MOS transistor is formed on a surface of the P-type semiconductor substrate 104. A gate conductor layer 108a for the P-channel MOS transistor and a gate conductor layer 108b for the N-channel MOS transistor are respectively formed on the gate oxide films 107a and 107b. On the left side and the right side of the gate conductor layer 108a for the P-channel MOS transistor, a drain P+ region 109a (hereinafter, a semiconductor region containing an acceptor impurity in a large amount is referred to as “P+ region”) and a source P+ region 109b are respectively formed on a surface of the N-well region 105. Similarly, on both sides of the gate conductor layer 108b for the N-channel MOS transistor, a drain N+ region 110b (hereinafter, a semiconductor region containing a donor impurity in a large amount is referred to as “N+ region”) and a source N+ region 110a are formed on a surface of the P-type semiconductor substrate 104. Furthermore, a first interlayer insulating layer 111 is formed, and contact holes 112a, 112b, 112c, and 112d are formed in the first interlayer insulating layer 111 on the P+ regions 109a and 109b and the N+ regions 110a and 110b, respectively. A power supply wiring metal layer Vdd formed on the first interlayer insulating layer 111 is connected to the drain P+ region 109a of the P-channel MOS transistor through the contact hole 112a. An output wiring metal layer Vo formed on the first interlayer insulating layer 111 is connected to the source P+ regions 109b of the P-channel MOS transistor and the source N+ region 110a of the N-channel MOS transistor through the contact holes 112b and 112c, respectively. A ground wiring metal layer Vss is connected to the drain N+ region 110b of the N-channel MOS transistor through the contact hole 112d. Furthermore, a second interlayer insulating layer 113 is formed. Contact holes 114a and 114b are formed in the second interlayer insulating layer 113 on the gate conductor layer 108a for the P-channel MOS transistor and the gate conductor layer 108b for the N-channel MOS transistor, respectively. Furthermore, an input wiring metal layer Vi formed on the second interlayer insulating layer 113 is connected to the gate conductor layer 108a for the P-channel MOS transistor and the gate conductor layer 108b for the N-channel MOS transistor through the contact holes 114a and 114b, respectively.
In this known example, in order to reduce a surface occupation area of the planar CMOS inverter circuit, it is necessary to reduce two-dimensional sizes of the gate conductor layer 108a for the P-channel MOS transistor, the gate conductor layer 108b for the N-channel MOS transistor, the source N+ region 110a and the drain N+ region 110b for the N-channel MOS transistor, the drain P+ region 109a and the source P+ region 109b for the P-channel MOS transistor, the contact holes 112a, 112b, 112c, 112d, 114a, and 114b when the surface of the P-type semiconductor substrate 104 is viewed from above. To achieve this, high-resolution processing techniques such as a lithography technique and an etching technique for further reducing a processing size are necessary.
In the planar MOS transistor, channels of the P-channel MOS transistor and the N-channel MOS transistor are disposed between the source and the drain so as to extend in the horizontal direction along surfaces of the P-type semiconductor substrate 104 and the N-well region 105. In contrast, channels of SGTs are disposed so as to extend in a direction perpendicular to a surface of a semiconductor substrate (refer to, for example, Japanese Unexamined Patent Application Publication Nos. 2-188966, and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)).
FIG. 15A is a structural schematic view of an N-channel SGT. As shown in FIG. 15A, N+ regions 116a and 116b are formed on upper and lower positions of a P-type or i-type (intrinsic) Si pillar 115 (hereinafter, a silicon semiconductor pillar is referred to as “Si pillar”). When one of the N+ regions 116a and 116b functions as a source, the other functions as a drain. When one of the N+ regions 116a and 116b functions as a drain, the other functions as a source. The Si pillar 115 located between the source/drain N+ regions 116a and 116b functions as a channel region 117. A gate insulating layer 118 is formed so as to surround the channel region 117. A gate conductor layer 119 is formed so as to surround the gate insulating layer 118. In the SGT, the source/drain N+ regions 116a and 116b, the channel region 117, the gate insulating layer 118, and the gate conductor layer 119 are formed in or on the single Si pillar 115. Therefore, the surface occupation area of the SGT apparently corresponds to a single source or drain N+ region of a planar MOS transistor. Accordingly, regarding circuit chips including SGTs, a further reduction in the chip size can be realized compared with circuit chips including planar MOS transistors.
FIG. 15B is a cross-sectional view of an inverter circuit having SGTs (refer to, for example, U.S. Pat. No. 8,188,537). As shown in FIG. 15B, an i-layer 121 (The term “i-layer” refers to an intrinsic Si layer, and an intrinsic Si layer is hereinafter referred to as “i-layer”.) is formed on an insulating layer substrate 120. A Si pillar SP1 for a P-channel SGT and a Si pillar SP2 for an N-channel SGT are formed on the i-layer 121. A source P+ region 122 of the P-channel SGT is formed in the i-layer 121 connected to a lower portion of the Si pillar SP1 for the P-channel SGT so as to be integrated with the i-layer 121 and to surround a lower portion of the Si pillar SP1. Similarly, a source N+ region 123 of the N-channel SGT is formed so as to be integrated with the i-layer 121 and to surround a lower portion of the Si pillar SP2. Furthermore, a drain P+ region 124 of the P-channel SGT is formed in an upper portion of the Si pillar SP1 for the P-channel SGT, and a drain N+ region 125 of the N-channel SGT is formed in an upper portion of the Si pillar SP2 for an N-channel SGT. Gate insulating layers 126a and 126b are formed so as to surround the Si pillars SP1 and SP2, respectively. A gate conductor layer 127a of the P-channel SGT and a gate conductor layer 127b of the N-channel SGT are formed so as to surround the gate insulating layers 126a and 126b, respectively. Insulating layers 128a and 128b are formed so as to surround the gate conductor layers 127a and 127b, respectively. The source P+ region 122 of the P-channel SGT is connected to the source N+ region 123 of the N-channel SGT through a silicide layer 129b. A silicide layer 129a is formed on the drain P+ region 124 of the P-channel SGT. A silicide layer 129c is formed on the drain N+ region 125 of the N-channel SGT. An i-layer 130a between the P+ regions 122 and 124 located in a lower portion and an upper portion of the Si pillar SP1 functions as a channel of the P-channel SGT. An i-layer 130b between the N+ regions 123 and 125 located in a lower portion and an upper portion of the Si pillar SP2 functions as a channel of the N-channel SGT.
Subsequently, a SiO2 layer 131 is formed by a chemical vapor deposition (CVD) method so as to cover the insulating layer substrate 120, the i-layer 121, and the Si pillars SP1 and SP2. Contact holes 132a, 132b, and 132c are formed in the SiO2 layer 131 on the Si pillar SP1, the Si pillar SP2, and the source P+ region 122 of the P-channel SGT and the source N+ region 123 of the N-channel SGT, respectively. A power supply wiring metal layer Vdd formed on the SiO2 layer 131 is connected to the drain P+ region 124 of the P-channel SGT and the silicide layer 129a through the contact hole 132a. An output wiring metal layer Vo formed on the SiO2 layer 131 is connected to the source P+ region 122 of the P-channel SGT, the source N+ region 123 of the N-channel SGT, and the silicide layer 129b through the contact hole 132b. Furthermore, a ground wiring metal layer Vss formed on the SiO2 layer 131 is connected to the drain N+ region 125 of the N-channel SGT and the silicide layer 129c through the contact hole 132c. Furthermore, the gate conductor layer 127a of the P-channel SGT and the gate conductor layer 127b of the N-channel SGT are connected to each other and connected to an input wiring metal layer (not shown). In this inverter circuit having SGTs, since the P-channel SGT and the N-channel SGT are respectively formed in the Si pillar SP1 and the Si pillar SP2, the circuit area when viewed from the vertical direction is reduced. As a result, the size of the inverter circuit can be further reduced as compared with an inverter circuit having planar MOS transistors in the related art.
Further reduction in the size of a circuit chip having SGTs is desired. To meet this need, it has been assumed that the circuit area when viewed from the vertical direction can be reduced by forming two SGTs in a single Si pillar SPa, as shown in a structural schematic view of FIG. 16 (refer to, for example, Hyoungjun Na and Tetsuo Endoh: “A New Compact SRAM cell by Vertical MOSFET for Low-power and Stable Operation”, Memory Workshop (IMW)-2011 3rd IEEE International Digest P1-P4 2011). As shown in FIG. 16, a CMOS inverter circuit is formed in which an N-channel SGT 133a is formed in a lower portion of the Si pillar SPa and a P-channel SGT 133b is formed on the N-channel SGT 133a. A drain N+ region 134a of the N-channel SGT 133a is formed in a lower portion of the Si pillar SPa and is connected to a ground terminal Vss. A channel i-layer 136a is formed on the drain N+ region 134a. A gate insulating layer 137a is formed on an outer peripheral portion of the channel i-layer 136a. A gate conductor layer 138a for the N channel SGT is formed on an outer peripheral portion of the gate insulating layer 137a. Furthermore, a source N+ region 134b is formed on the channel i-layer 136a. A source P+ region 135a of the P-channel SGT 133b is formed on the source N+ region 134b so as to be in contact with the source N+ region 134b. A channel i-layer 136b is formed on the source P+ region 135a. A gate insulating layer 137b is formed on an outer peripheral portion of the channel i-layer 136b. A gate conductor layer 138b used for the P-channel SGT 133b is formed on an outer peripheral portion of the gate insulating layer 137b—. Furthermore, a drain P+ region 135b is formed in a top portion of the Si pillar SPa, the top portion being located on the channel i-layer 136b. The drain P+ region 135b is connected to a power supply terminal Vdd. The gate conductor layer 138a of the N-channel SGT 133a and the gate conductor layer 138b of the P-channel SGT 133b are connected to an input terminal Vi. The source N+ region 134b of the N-channel SGT 133a and the source P+ region 135a of the P-channel SGT 133b are connected to an output terminal Vo.
Referring to FIG. 16, in the case where an SGT inverter circuit is formed in the single Si pillar SPa, a problem of difficulty of manufacture occurs. It is necessary to form the source P+ region 135a of the P-channel SGT 133b and the source N+ region 134b of the N-channel SGT 133a so that the source P+ region 135a and the source N+ region 134b are disposed in the middle of the Si pillar SPa and are in contact with each other. In the case where the planar MOS transistor circuit in the related art shown in FIG. 14 is produced, the N+ regions 110a and 110b and the P+ regions 109a and 109b can be formed by an ion implantation method in which accelerated donor and acceptor impurity ions are implanted from an upper surface of the P-substrate 104 using, as a mask, a photoresist layer formed by using an existing photolithographic technique. Similarly, in the case where the inverter circuit having SGTs and shown in FIG. 15B is formed, the N+ region 123 and the P+ region 122 can be formed by an ion implantation method in which accelerated donor and acceptor impurity ions are implanted from an upper surface of the insulating layer substrate 120 using, as a mask, a photoresist layer formed by using a photolithographic technique. In contrast, referring to FIG. 16, in the case where an inverter circuit is formed in the single Si pillar SPa, the N+ region 134b and the P+ region 135a cannot be formed by the ion implantation method used in the related art. This is because ions cannot be implanted from a horizontal direction into a side face of the Si pillar by the ion implanting method used in the related art. Instead of this method, the following method is conceivable: A donor or acceptor impurity is diffused into a Si pillar SPa by diffusing from, for example, a poly-Si or SiO2 film that contains the donor or acceptor impurity into a side face near the middle of the Si pillar SPa. For this purpose, the whole Si pillar SPa is covered with a diffusion stopper film, and part of the diffusion stopper film located in a portion to be diffused is then removed. Subsequently, an impurity diffusion film is deposited, and heat treatment is performed to form the N+ region 134b and the P+ region 135a. In this case, the N+ region 134b and the P+ region 135a cannot be formed at the same time, and thus it is necessary to form the N+ region 134b and the P+ region 135a separately. Therefore, it is difficult to form the N+ region 134b and the P+ region 135a in the vertical direction with a high accuracy.
Furthermore, producing an SGT circuit having a structure in which both an N-channel SGT and a P-channel SGT are provided in a lower portion and both an N-channel SGT and a P-channel SGT are further provided in an upper portion further increases the difficulty of manufacture, for example, as in the case where the structure shown in FIG. 17A, in which a P-channel SGT 139a is formed in a lower portion of a single Si pillar SPb and an N-channel SGT 139b is formed on the P-channel SGT 139a, and the structure shown in FIG. 17B, in which an N-channel SGT 140a is formed in a lower portion of a single Si pillar SPc and an N-channel SGT 140b having the same structure as the N-channel SGT 140a is further formed on the N-channel SGT 140a, are formed.